In order to improve the power factor of the ballast circuit, it is well known to employ a power factor correction (PFC) circuit. Power factor is defined as the real input power level divided by the apparent power level, wherein the apparent power is defined as the RMS voltage value multiplied by the RMS current value. Thus, a system with a low power factor rating is more expensive to operate since it requires larger input current for a given real power in comparison to a system with a higher power factor. In addition, in ballast circuits with a low power factor rating the components within the ballast circuit generally have a higher power and increased size in order to handle the higher currents associated with systems having a low power factor. PFC circuitry is also used to reduce the harmonics which are coupled back onto the AC input line by the ballast circuit. There are many single stage ballast circuit topologies. Most of these circuit topologies can be classified into boost circuits, charge pump circuits, or a mix of both boost and charge pump.
The single stage boost circuit combined with an inverter is described in U.S. Pat. Nos. 4,564,897, 5,001,400 and 5,434,477. In these circuits, the boost section is used to shape the input current and the inverter section is used to convert the DC bus voltage into high frequency AC as the output for a AC-DC-AC converter. That is, the boost circuit controls the input current and the inverter controls the circuit output characteristics. Generally, the input current to the boost circuit is discontinuous. In a discontinuous current mode, it is not necessary to have a current feedback loop, stability problems are eliminated, and the line current is nearly sinusoidal. Additionally, there are no diode reverse recover problems which happen in continuous current mode and the switching power loss is relatively low. Furthermore, since a portion of the current is fed directly to the DC bus, the efficiency of the boost circuit is relatively high. However, since only a portion of the current flows through the switch (e.g., a FET) in the inverter, it is difficult to control the total harmonic distortion (THD) as the DC bus voltage in the ballast circuit approaches the peak voltage of the line.
In the single stage boost circuit, the switch components within the inverter section play two roles. First, to shape the input current, and second to control the output. In order to keep the output modulation low, the duty-cycle of the switch must be constant. However, this causes a high voltage stress on the switches and other components because in order to remain in the discontinuous current mode, the switch voltage must be at least twice the peak input voltage when the duty cycle is 50%. For example, with an AC line voltage of 277 Vrms (390 V peak) the voltage stress on the inverter switches will be about 800 V.
The charge pump circuits described in U.S. Pat. Nos. 5,459,651, 5,404,082, 5,410,221, and 5,488,269, Japanese Patent 8-186981, and in the paper entitled "Investigation of Charge-Pump-Controlled High Power Factor Correction AC-DC Converter" presented by Jinrong Qian and Fred C. Lee, disclose replacing the boost inductor with a capacitor. Charge pump circuits employ a high-frequency source to shape the line current and improve the THD. In a charge pump circuit, the DC bus voltage within the ballast circuit can approach the peak input voltage value, greatly decreasing the voltage stress on the inverter switches. However, the current stress on the switches increases because the switches must also handle the charge pump current.
A combination boost and charge pump circuit was disclosed by Professor Chin S. Moo at the Applied Power Electronics Conference in 1996. This circuit combines some of the advantages of the boost and charge pump circuits. The input current is partly continuous and partly discontinuous because the circuit works in both boost and charge pump modes depending upon the line input voltage level. During the boost mode, a portion of the input energy is fed directly to the DC bus of the ballast circuit. This lowers the energy storage requirements of the input capacitors, and decreases the amount of power handled by the charge pump, thereby decreasing the output modulation and lowering the current stress on the switches.
Since the combination circuit is also a charge pump, the DC bus voltage can be operated close to the input peak voltage in order to decrease the voltage stress on the inverter switches. The switches are controlled by dead-off time in order to avoid hard switching and to reduce the power loss associated with hard switching of the switches. However, this prior art technique is a relatively complicated control technique since the timing of the switches (e.g., the dead-off time) must be accurately controlled, thus increasing the cost of the control circuitry and the overall cost of the electronic ballast circuit.
Therefore, there is a need for an improved electronic ballast circuit having reduced complexity and improved switching characteristics such as softer switching.